1. Field of the Invention
The present invention relates to a method of and device for driving a plasma display panel including cells defined at respective points of intersection of a plurality of electrodes.
2. Description of the Background Art
FIG. 26 is a schematic diagram of a plasma display device disclosed in, for example, U.S. Pat. No. 5,446,344 (8/1995) (first prior art). The reference numeral 101 designates a display panel which comprises a first glass substrate serving as a first substrate, sustain electrodes X as first electrodes and scan electrodes Y1 to Yn as second electrodes which are formed on the first glass substrate and arranged in parallel, a second glass substrate opposed to the first glass substrate and serving as a second substrate, and address electrodes A1 to Am as third electrodes which are formed on the second glass substrate and arranged in a direction perpendicular to the sustain electrodes X and the scan electrodes Y1 to Yn.
The plasma display device includes n.times.m pixels. A discharge cell is defined at a point of intersection of any scan electrode Yi (i=1 to n) and any address electrode Aj (j=1 to m). The scan electrodes Y1 to Yn and the address electrodes A1 to Am are insulated from and independent of each other for individual drive so that address selection for switching on/off is made for each of the defined discharge cells.
The sustain electrodes X are paired with the scan electrodes Y1 to Yn respectively, and have respective first ends connected commonly. Voltages in the form of pulses of first to fourth voltages to be applied to these electrodes are generated in a power supply circuit 102 and supplied to the electrodes through a Y sustain driver 103, a scan driver 104, an X sustain driver 105, and an address driver 106. The Y sustain driver 103, the scan driver 104, the X sustain driver 105, and the address driver 106 are controlled by respective control signals from a control circuit 107. The control circuit 107 generates the control signals based on display data (DATA in FIG. 26) supplied from the exterior, a dot clock (CLK in FIG. 26) in synchronism with the display data, a vertical synchronizing signal (VSYNC in FIG. 26), and a horizontal synchronizing signal (HSYNC in FIG. 26).
FIG. 27 is a sectional view of a cell of a plasma display panel. In FIG. 27, the reference characters X and Yi designate a pair of sustain and scan electrodes formed on a glass substrate 108 serving as the first substrate and extending in the direction perpendicular to the plane of the figure; 109 designates a dielectric layer (for holding a wall charge) formed on the pair of sustain and scan electrodes X and Yi; 110 designates a protective layer formed on the surface of the dielectric layer 109; Aj designates an address electrode formed on a glass substrate 111 as the second substrate opposed to the glass substrate 108, and extending in the lateral direction of the plane of the figure; 112 designates a phosphor formed on the address electrode Aj; 113 designates barrier ribs formed on the boundaries of pixels; and 114 designates a discharge space between the protective layer 110 and the phosphor 112 which is filled with a Penning gas mixture of neon ion (Ne.sup.+) and xenon, for example.
Operation is described hereinafter.
FIGS. 28(a) through 28(f) illustrate applied voltage waveforms showing a conventional method of driving a plasma display device. In FIGS. 28(a) through 28(f), a reset step, a write step, and a sustain discharge step are shown in chronological order.
Referring to FIGS. 28(a) through 28(f), in the reset step, a priming pulse 121 serving as a pulse of the first voltage is applied between the sustain electrode X and the scan electrode Yi to produce a gas discharge between the sustain electrode X and the scan electrode Yi, thereby generating a space charge in the discharge space 114 and accumulating a wall charge which allows a wall voltage higher than a firing voltage to be generated. Next, a self-erase discharge is caused to occur at the falling edge of the priming pulse 121 to place the cell into a charge erased condition (wherein the accumulated charge in the dielectric layer 109 on the sustain electrode X and the scan electrode Yi equals zero).
Next, in the write step, a scan pulse 122 is applied sequentially to the scan electrodes Y1 to Yn, and address pulses are applied to the address electrodes A1 to Am in accordance with the display data, whereby the second voltage is developed between the address electrodes A1 to Am and the scan electrodes Y1 to Yn to initiate a write discharge.
Then, in the sustain discharge step, a sustain pulse is alternately applied between the sustain electrode X and the scan electrode Yi (the fourth voltage is alternately applied between the sustain electrode X and the scan electrode Yi) to maintain the gas discharge.
The first voltage used herein is a potential difference between the sustain electrode X and the scan electrode Yi. In FIGS. 28(b) through 28(e), the scan electrode Yi is at zero potential, and a pulse at a potential Vpf is applied to the sustain electrode X. Therefore, the potential Vpf equals the first voltage. Alternatively, a pulse at a potential Vp .alpha. and a pulse at a negative potential Vp .beta. (where (first voltage)=Vp .alpha.-Vp .beta.), for example, may be applied to the sustain electrode X and the scan electrode, respectively, as will be described later.
Similarly, the second voltage is a potential difference between the address electrode Aj and the scan electrode Yi. (In FIGS. 28(a) through 28(f), Va-Vsp=(second voltage). This may be expressed as .vertline.Va.vertline.+.vertline.Vsp.vertline.=(second voltage) since the potential Vsp is a negative potential.)
The fourth voltage is a potential difference between the sustain electrode X and the scan electrode Yi (Vcc=(fourth voltage) in FIGS. 28(b) through 28(e)).
The above described reset step, write step, and sustain discharge step are sequentially repeated for display operation.
With reference to FIGS. 29(a.sub.0) through 29(f.sub.0), state changes within a cell in the reset step are described below. FIGS. 29(f) through 29(f.sub.0) correspond to time periods (a) to (f) shown in FIG. 28(f), respectively. After the end of the preceding drive cycle, predetermined amounts of wall charges having opposite polarities are accumulated in portions corresponding to the sustain electrode X and the scan electrode Yi which are adjacent to each other, respectively (FIG. 29(a.sub.0)). In this state, when the priming pulse 121 is applied between the sustain electrode X and the scan electrode Yi, a gas discharge is initiated between the sustain electrode X and the scan electrode Yi (FIG. 29(b.sub.0)). Electrons and positive ions generated by the gas discharge are attracted toward the opposite-polarity sustain electrode X and scan electrode Yi respectively and accumulated on the surface of the dielectric layer 109 to act as respective wall charges associated with the sustain electrode X and scan electrode Yi. Since these wall charges reduce the electric field strength in the discharge space, the gas discharge immediately converges to a termination (FIG. 29(c.sub.0)).
Next, when the application of the priming pulse 121 to the sustain electrode X and the scan electrode Yi is stopped, the wall charges initiate a gas discharge between the sustain electrode X and the scan electrode Yi (FIG. 29(d.sub.0)). Then, the positive ions and the electrons recombine together (FIG. 29(e.sub.0)), resulting in the reduction in wall charges (FIG. 29(f.sub.0)).
In the reset step, the priming pulse 121 (entire write pulse) applied between the sustain electrode X and the scan electrode Yi performs the following functions:
(a) To force a gas discharge to occur once to reset the charges into a relatively uniform state independently of the previous display state.
(b) To generate a space charge to render a subsequent gas discharge easy to occur.
(c) To cause an erase operation (to return all discharge cells into an erase state, that is, a state wherein there is no accumulated charge).
The PDP (plasma display panel) is a capacitive load in structural terms. When the sustain pulse is applied to the load, a reactive power is generated by charging and discharging a capacitance element of the panel (refereed to hereinafter as a panel capacitance). U.S. Pat. No. 5,081,400 (1/1992) as a second prior art technique discloses a sustain pulse generating circuit as shown in FIG. 30 (illustrating an X sustain driver connected to a sustain electrode X and a Y sustain driver connected to a scan electrode Yi) which comprises a capacitor 10 and an inductor 11 for recovery of the reactive power by utilizing the LC resonance of a panel capacitance 12 and the inductor 11.
Next, how the circuit shown in FIG. 30 operates will be described with reference to FIGS. 31(a) and 31(b).
State (1)
Initially, switch elements S2, S3 and S4 are opened, and a switch element S1 is closed. Then, a charging current flows from the capacitor 10 charged up to a voltage Vss through the inductor 11 to the static capacitance element 12 of the display panel 101. At this time, the inductor 11 and the static capacitance element 12 form a series resonant LC circuit, and a panel voltage Vp rises up to a voltage expressed by 2.times.Vss. Since Vss=Vcc/2, the panel voltage Vp rises up to a power supply voltage Vcc which is a sustain pulse voltage. At this point of time, current I.sub.L flowing through the inductor 11 equals zero.
It should be noted that the panel voltage Vp means a potential difference between the electrodes X and Yi, that is, a voltage applied to the display panel at a certain instant. Therefore, the panel voltage Vp is expressed as a function of time t in the form of Vp(t).
State (2)
The switch element S3 is closed to hold the panel voltage Vp at the power supply voltage Vcc. A gas discharge current is fed through the switch element S3 to the display panel.
State (3)
The switch elements S1 and S3 are opened, and the switch element S2 is closed. The inductor 11 and the static capacitance element 12 again form a series resonant circuit, and the panel voltage Vp drops to a ground level. At this point of time, the current I.sub.L equals zero.
State (4)
The switch element S4 is closed to hold the panel voltage Vp at the ground level.
Subsequently, the driver (Y sustain driver) which is provided on the opposite side of the panel from the X sustain driver in a symmetrical manner performs similar operations in States (1) to (4).
In the above described operations, the switch elements S3 and S4 function to clamp and hold the panel voltage Vp at the power supply voltage Vcc or the ground level. Accordingly, the switch elements S3 and S4 are referred to hereinafter as clamp switches.
This prior art structure is characterized in that when the current I.sub.L flowing through the inductor 11 reaches zero, the clamp switch S3 or S4 is switched on to hold the panel voltage Vp at the power supply voltage Vcc or the ground level. Specifically, the panel voltage Vp is at a maximum level (or a minimum level) when the current I.sub.L flowing through the inductor 11 reaches zero. At this point of time, the clamp switch S3 or S4 is switched on to maximize the efficiency of power recovery (ideally 100%). An ideal operation without power losses is described above. FIG. 32 is an equivalent diagram of a practical plasma display panel and circuit for driving the same. Power losses in resistance elements R1, Rd1, R2, Rd2, R.sub.L in the circuit and some losses resulting from the presence of additional static capacitance elements c1, c2, cd1, cd2 which do not contribute to the recovery are caused.
Most of the losses in the plasma display device are caused in the resistance elements. FIG. 33 is an equivalent diagram of a series resonant LCR circuit which may be considered by significant simplification of the plasma display panel and circuit for driving the same shown in FIG. 32. In this case, the increase in power losses may be treated as the decrease in Q-value in the series resonant LCR circuit.
As a result, an output voltage does not reach the power supply voltage Vcc only by charging the panel capacitance element using the LC series resonance discussed in State (1), that is, by charging caused by the transfer of energy accumulated in the inductor 11. As shown in FIGS. 34(a) and 34(b), the panel voltage Vp exhibits two-step changes: the series resonant LC circuit causes the panel voltage Vp to once reach a voltage V1 determined by the Q-value thereof, and controlling the switch element S3 to be in the on state at this time causes the panel voltage Vp to reach the voltage Vcc.
The reactive power recovery efficiency in the above described circuit shown in FIG. 33, that is, the proportion of the recovered power to the reactive power caused by the panel capacitance 12 is expressed approximately as V1/Vcc.
This is explained using expressions to be described below. The reactive power P0 caused by the panel capacitance 12 having a capacitance value Cp is expressed as EQU P0=f.times.Cp.times.Vcc.sup.2
where f is the frequency of charging and discharging per unit time, and the power P1 supplied from the power supply is expressed as EQU P1=.intg.(Vcc.times.i(t)) dt=Vcc.times.f.times.Cp.times.(Vcc-V1)
Thus, the reactive power recovery efficiency is expressed as EQU 1-P1/PO=V1/Vcc
The increase in reactive power recovery efficiency in the above described circuitry requires the increase in the Q-value of the resonant LC circuit. For the increase in the Q-value of the resonant LC circuit, any one of the following requirements should be satisfied:
(a) To set the inductance L of the inductor 11 to a level higher than the conventional inductance.
(b) To decrease the value Cp of the panel capacitance 12.
(c) To decrease the resistance element.
For the requirement (b), the value Cp of the panel capacitance 12 is determined by, the plasma display panel acting as the load and, thus, very difficult to decrease.
For the requirement (c), the resistance element is determined by the resistances of the components to be used and the resistances of the electrodes in the plasma display panel, and the decrease in the resistance element leads to a significant increase in costs.
For the requirement (a), setting the inductance to a relatively high level is very effective in practical terms. However, the setting of the inductance to a relatively high level to increase the Q-value of the resonant LC circuit in the case where the circuit of FIG. 33 is used for a plasma display device presents another problem that is adverse effects upon the gas discharge as will be described later.
The above-mentioned problem is described below with reference to FIGS. 35(a) and 35(b).
As illustrated in State (1), the panel voltage Vp rises up to the voltage to be reached (first level) V1 which is determined in accordance with the setting of the Q-value of the resonant LC circuit. At this time, if the first level V1 exceeds a firing voltage Vf and a rise time greater than a discharge delay time is required, a gas discharge is initiated on the panel before the transition to State (2). During the time represented by State (1), current is supplied through the inductor 11 in the resonant LC circuit to the plasma display panel, providing a very high output impedance in principle. When a gas discharge current flows to the plasma display panel in this state, the input impedance of the panel decreases, but the output impedance of the circuit remains high. Then, the panel voltage Vp abruptly decreases as shown by the dotted curve of FIG. 35(a), resulting in the effective decrease in applied voltage. This consequently decreases the intensity of the gas discharge to reduce a display luminance, and causes the wall charges to vanish, failing to continue the sustain discharge.
For reference purposes, FIG. 36 schematically shows how the rising edge of the panel voltage Vp changes depending upon the set value of the inductance L of the inductor 11. The curves C1, C2 and C3 of FIG. 36 show the waveforms of the panel voltage Vp when the inductance L is set to three values L1, L2 and L3, respectively, where L1&lt;L2&lt;L3. The curve C1 shows the waveform at the highest resonance frequency and, accordingly, exhibits the highest rate of rise at the rising edge (the lowest Q-value), but reaches the lowest level (first level) V1.
In contrast, when the inductance L is set to the value L3, the resonance frequency is the lowest and the Q-value is the highest. Then, the rate of rise at the rising edge of the panel voltage Vp is the lowest, and the panel voltage Vp changes slowly. The first level V1 at this time is the highest. Thus, as the inductance L is changed to a higher value such as during a transition from the curve C1 to the curve C3, the first level V1 on the increase approaches the firing voltage Vf and exceeds the firing voltage Vf in the course of time. A gas discharge is initiated before the panel voltage Vp reaches the pulse voltage Vcc which is the power supply voltage. In the case of the curve C3, in particular, if the panel voltage Vp is still rising slowly toward the first level V1 after an elapse of the gas discharge delay time to be described later since the point of time where Vp=Vf, a gas discharge is initiated before the panel voltage Vp reaches the first level V1, resulting in the change of the curve C3 as indicated by the broken curve of FIG. 35(a).
The firing voltage Vf is defined to mean a minimum voltage applied between the first and second (X, Y) electrodes when the gas discharge is actually initiated. The sum of the voltage developed by the wall charge and the firing voltage Vf corresponds to a gas discharge starting voltage in the discharge space 114 of FIG. 27. Strictly speaking, the gas discharge does not occur as soon as voltage is applied to the display panel but is initiated after some delay time. Therefore, the firing voltage Vf varies depending on the rate of change in panel voltage or the rising rate of the panel voltage.
Whether or not the discharge is initiated during the time illustrated in State (1) depends on the following two factors:
(i) The rate of voltage change at the rising edge or the rising rate in the resonant LC circuit (the rising rate if it is low is disadvantageous). (ii) The level reached by the voltage using the resonant LC circuit (that is, the first level V1 of FIG. 35(a); the first level if it is high is disadvantageous).
Which one of the two factors is a more significant problem depends on the relationship between the rising rate of the panel voltage Vp and the discharge delay time (typically about 100 to 500 ns).
Increasing the inductance L of the inductor 11 for the purpose of increasing the Q-value of the resonant LC circuit for high recovery efficiency causes a slow rise of the panel voltage Vp to reflect the problem of the factor (i), and also increases the first level V1 during the charging of the panel to reflect the problem of the factor (ii). In either case, the prevention of the adverse effects upon the gas discharge on the panel requires the reactive power recovery efficiency to be somewhat sacrificed.
In this manner, there exists a tradeoff between the enhancement of the power recovery efficiency by the increase in Q-value and the maintenance and improvement of the discharge characteristics in the panel.
To solve the tradeoff problem, technique disclosed in Japanese Patent Application Laid-Open No. P05-265397A (1993) (a third prior art) employs separate inductors provided respectively for the rising and falling edges of a pulse. In this technique, the inductors are interchanged for use at the rising and falling edges so that the pulse rises fast and falls slowly. This arrangement, however, requires the separate inductors for respective use at the rising edge and falling edge of the pulse to result in the increased number of parts and the increased complexity of the structure, creating another problem of high costs.
Additionally, this technique does not solve the problem of the factor (ii). If the rising rate is not sufficiently faster than the delay time of gas discharge initiation, the recovery efficiency is not increased above a certain level due to the limitation of the factor (ii).
The prior art plasma display devices constructed as above described have found difficulties in increasing the reactive power recovery efficiency to a certain level or higher without adverse effects upon the gas discharge in the plasma display panel.